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  智力抢答器源程序
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  • 作者:qdq
  • 时间:2005/11/1 21:40:25
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count10 is
port( clk:in std_logic; --1hz
en:in std_logic;
clr:in std_logic;
up,dn:in std_logic;
dout:out std_logic_vector(3 downto 0)
);
end count10;

architecture behav of count10 is
signal q:integer range 0 to 9;

begin

process(clk,clr)
begin
if clr='1' then q<=3;
elsif clk'event and clk='1' then
if en='1' then
if up='1' then
if q<9 then q<=q+1;
else q<=3;end if;

elsif dn='1' then
if q>0 then q<=q-1;
else q<=3;end if;
end if;

end if;
end if;
end process;

dout<=conv_std_logic_vector (q,4);
end behav;
--*************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--**************************************************************
ENTITY Debunce is
PORT(
CP : IN STD_LOGIC; -- CLOCK 4MHZ
Key : IN STD_LOGIC; -- Input Signal
DOUT : OUT STD_LOGIC -- Debounce O/P

);
END Debunce;

--**************************************************************
ARCHITECTURE a OF Debunce IS
SIGNAL SAMPLE, DIFF,DLY_OUT: STD_LOGIC; -- Binary
BEGIN

Free_Counter : Block -- 计数器 & 产生扫描信号
Signal Q : STD_LOGIC_VECTOR(14 DOWNTO 0);
Signal D0 : STD_LOGIC;
Begin

PROCESS (CP) -- 计数器计数
Begin
IF CP'Event AND CP='1' then
D0 <= Q(14);
Q <= Q+1;
END IF;
END PROCESS;

SAMPLE <= Q(14) AND NOT D0; --产生125HZ脉冲?
END Block Free_Counter;


Debounce : Block -- Timer Key Debounce
SIGNAL D0, D1, S, R,DLY,NDLY : STD_LOGIC;
Begin
Process (CP)
Begin
IF CP'EVENT AND CP='1' THEN
IF SAMPLE = '1' THEN
D1 <= D0; D0 <=NOT Key; --二级延迟
S <= D0 AND D1;
R <= NOT D0 AND NOT D1;
END IF;
END IF;
End Process;
DLY <= R NOR NDLY; --RS 触发器
NDLY <=S NOR DLY;
DLY_OUT <= DLY; --RS 触发器输出

End Block Debounce;

Differential : Block
Signal D1,D0 : STD_LOGIC;
BEGIN
Process (CP)
Begin
IF CP'EVENT AND CP='1' THEN
D1 <= D0; D0 <= DLY_OUT; --二级延迟
END IF;
End Process;
DIFF <= D0 AND NOT D1; --微分
END Block Differential;

DOUT<= DIFF AND NOT Key;
END A;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity decled is
port(din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(6 downto 0)
);
end decled;

architecture behav of decled is

begin

process(din)
begin
case din is
when "0000"=>dout<="0111111";
when "0001"=>dout<="0000110";
when "0010"=>dout<="1011011";
when "0011"=>dout<="1001111";
when "0100"=>dout<="1100110";
when "0101"=>dout<="1101101";
when "0110"=>dout<="1111101";
when "0111"=>dout<="0000111";
when "1000"=>dout<="1111111";
when "1001"=>dout<="1101111";
when others=>dout<="0000000";
end case;
end process;

end behav;

library IEEE;
use IEEE.std_logic_1164.all;

entity sound is
port (
soundclk: in STD_LOGIC; --1024HZ
soundctrl: in STD_LOGIC;
speaker: out STD_LOGIC
);
end sound;

architecture sound_arch of sound is
begin
speaker<=soundclk and soundctrl;
end sound_arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity zlqdq is
port(clk:in std_logic; --4MHz
key:in std_logic_vector(3 downto 0); --4组抢答键
clr:in std_logic; --系统清零 键
start:in std_logic; --开始键,复位键
startled:out std_logic; --开始标志
wrong:in std_logic; --减分键
wled:out std_logic; --减分标志
right:in std_logic; --加分键
rled:out std_logic; --加分标志
selout:out std_logic_vector(5 downto 0);--扫描信号
segout:out std_logic_vector(6 downto 0);--数码显示
ring:out std_logic --响铃信号
);
end zlqdq;

architecture behav of zlqdq is
component Debunce --消除弹跳
PORT(
CP : IN STD_LOGIC; -- CLOCK 4MHZ
Key : IN STD_LOGIC; -- Input Signal
DOUT : OUT STD_LOGIC -- Debounce O/P

);
END component;
component count10 --可控加减计数器
port(clk:in std_logic; --1hz
en:in std_logic;
clr:in std_logic;
up,dn:in std_logic;
dout:out std_logic_vector(3 downto 0)
);
end component;
component decled --BCD 转换成七段译码
port(din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(6 downto 0)
);
end component;
component sound --响铃模块
port (
soundclk: in STD_LOGIC; --1953HZ
soundctrl: in STD_LOGIC;
speaker: out STD_LOGIC
);
end component;
signal q:std_logic_vector(21 downto 0); --自由计数器计数信号
signal cp,cp1,soundclk,r,r1,r2:std_logic; --1hz和 响铃频率和 响铃信号

signal clr1,clr2,clr3,el,sta,up,dn,cl,up1,dn1:std_logic;
signal k,en1,d3,d4,d5:std_logic;
signal s:std_logic_vector(2 downto 0);
signal ec,ec1,ec2,en:std_logic_vector(3 downto 0);
signal bin,d1,d0,db1,db2,db3,db4,time:std_logic_vector(3 downto 0);
signal m,qq:integer range 0 to 9;
begin

process(clk) --自由计数器
begin
if clk'event and clk='1' then
q<=q+1;
end if;
end process;

cp<=q(21);cp1<=q(20); --1hz
s<=q(15 downto 13); --250hz
startled<=el; --开始标志
rled<=up1; --加分标志
wled<=dn1; --减分标志
soundclk<=q(10); --1953hz
time<=conv_std_logic_vector(m,4); --倒计时时间
r<=r1 or r2; --响铃信号
clr3 <=not el ; --倒计时清零信号
cl<=not clr; --系统清零信号
k<=el and en1; --锁存器锁存使能

en<="0001" when ec1="0001" else --抢答后显示组号
"0010" when ec1="0010" else
"0011" when ec1="0100" else
"0100" when ec1="1000" else
"0000";

selout<="000001" when s=0 else --扫描信号
"000010" when s=1 else
"000100" when s=2 else
"001000" when s=3 else
"010000" when s=4 else
"100000" when s=5 else
"000000";

bin<= db1 when s=0 else --轮显选择
db2 when s=1 else
db3 when s=2 else
db4 when s=3 else
time when s=4 else
en when s=5 else
"0000";

gen:for i in 0 to 3 generate
u1:debunce port map(clk,key(i),ec(i)); -- 抢答键消除弹跳
end generate gen;
u2:sound port map(soundclk,r,ring);
u3:debunce port map(clk,start,sta);
u4:debunce port map(clk,wrong,dn);
u5:debunce port map(clk,right,up);
u6:count10 port map(cp,ec2(0),cl,up1,dn1,db1);
u7:count10 port map(cp,ec2(1),cl,up1,dn1,db2);
u8:count10 port map(cp,ec2(2),cl,up1,dn1,db3);
u9:count10 port map(cp,ec2(3),cl,up1,dn1,db4);
u0:decled port map(bin,segout);

process(el) --计数器使能控制
begin
if el'event and el='0' then
ec2<=ec1;
end if;
end process;

process(clk) --开始抢答信号
begin
if clk'event and clk='1' then
if sta='1' then
el<=not el;
end if;
end if;
end process;

process(clk) --加分使能
begin
if clk'event and clk='1' then
if up='1' then
up1<=not up1;
end if;
end if;
end process;

process(clk) --减分使能
begin
if clk'event and clk='1' then
if dn='1' then
dn1<=not dn1;
end if;
end if;
end process;


process(cp1,ec1) --按键后发声信号
begin
if ec1="0000" then qq<=0;
elsif cp1'event and cp1='1' then
if ec1>0 and el='1' then
if qq=0 then r2<='1';
else r2<='0';end if;
qq<=qq+1;
end if;
end if;
end process;

process(ec1) --锁存控制信号
begin
if ec1>0 then en1<='1' ;
else en1<='0';
end if;
end process;


process(clk) --锁存器
begin
if clk'event and clk='1' then
d4<=d3;d3<=el;
if el='1' then
if k='0' then
d1<=d0;d0<=ec;
end if;
end if;
end if;
end process;
d5<=not (el and not d4);
ec1<=d1 when d5='1' else
"0000";


process(cp) --到计时及发声模块
begin
if clr3='1' then m<=9;
elsif cp'event and cp='1' then
if el='1' then
if m>0 then m<=m-1;
else m<=9;
end if;
else m<=9;
end if;
end if;
if m=0 then
r1<='1';
else r1<='0';
end if;
end process;

end behav;

 

 

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